This invention is related to an integrated circuit having an I.sup.2 L, integrated inverted logic, transistor and a bipolar power transistor, and more particularly to such an integrated circuit having two epitaxial layers wherein the emitter of the I.sup.2 L transistor includes an N.sup.+ N holes-barrier junction.
It is known to make an integrated circuit with two epitaxial layers wherein a power transistor is formed in one epitaxial pocket and an inverted I.sup.2 L transistor is formed in another. A lower buried layer at the substrate is substantially spaced from the base of the power transistor to provide in the power transistor a high BV.sub.CEO. An upper buried layer at the interface of the two epitaxial layers reaches the depletion region of the forward biased base-emitter junction to obtain enhanced up-gain by the conventional mechanisms of increasing the ratio of the impurity concentrations in the emitter and base, respectively. This ratio and thus the up-gain of such prior art I.sup.2 L transistors is subject to change as a function of variations in the upper epitaxial growth step and the impurity doping and driving steps needed to form other regions in the integrated circuit. The bases of all the transistors are simultaneously formed in one masking and one impurity diffusion step. Also, the power transistor emitter is formed simultaneously with the collector(s) of the inverted transistor.
In the practice of the aforementioned prior art, the control of the depth of the power transistor emitters and inverted transistor collectors tends to be critical and a compromise is made whereby the base width in the power transistor must remain large enough to prevent punch through and the approximately same base width in the inverted transistor must be shallow enough to provide adequate up-current gain in the inverted transistor. This problem is partially overcome by establishing the upper buried layer closely adjacent to the base of the inverted transistor and by using a fast diffusing n-type impurity (e.g. phosphorous) in the upper buried layer, to diminish the base width and to increase the aforementioned up-gain, but thereby entailing even more precise control of the process. The actual breakdown voltage BV.sub.CEO of the power transistor in many instances must be made close to the intended operating collector voltage while the gain of the inverted transistor is just sufficient to insure reliable I.sup.2 L gate operation. More generally the extent of impurity diffusions, impurity concentrations, and the upper buried layer thicknesses all tend to be critical.
It is an object of this invention to provide an improved method for making an integrated circuit having a power transistor and an I.sup.2 L transistor with higher yields or requiring less critical controls in manufacturing or both.
It is another object of this invention to provide an integrated circuit having a power transistor and an I.sup.2 L transistor wherein at the base emitter transition there is a PNN.sup.+ double barrier junction.
It is a further object of this invention to provide an improved method for making such an integrated circuit wherein the BV.sub.CEO of the power transistor and the up-current gain of the inverted transistor may be controlled by relatively independent process steps.
It is yet a further object of this invention to use high resistivity epitaxial layers for providing high BV.sub.CEO power transistors while also providing adequate up-gain in the I.sup.2 L transistors.